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freescale semiconductor data sheet: technical data ? freescale semiconductor, inc., 2006, 2007. all rights reserved. freescale reserves the right to change the deta il specifications as may be required to permit improvements in the design of its products. DSP56720 / dsp56721 DSP56720 144-pin lqfp 20 mm x 20 mm 0.5 mm pitch dsp56721 80-pin lqfp 14 mm x 14 mm 0.65 mm pitch 144-pin lqfp 20 mm x 20 mm 0.5 mm pitch ordering information device device marking or operating temperature range lqfp package DSP56720 dspa56720ag 20 mm x 20 mm dspb56720ag 20 mm x 20 mm DSP56720 dspa56721ag 20 mm x 20 mm dspb56721ag 20 mm x 20 mm dspa56721af 14 mm x 14 mm dspb56721af 14 mm x 14 mm document number: DSP56720 rev.1, 12/2007 the symphony DSP56720/dsp56721 multi-core audio processors are part of the dsp5672x family of programmable cmos dsps, designed using multiple dsp56300 24-bit cores. the DSP56720/dsp56721 devices are intended for automotive, consumer, and professional audio applications that require high performance for audio processing. in addition, the DSP56720 is ideally suited for applications that need the capability to expand memory off-chip or to interface to external parallel peripherals. potential applications include a/v receivers, hd-dvd and blu-ray players, car audio/amplifiers, and professional recording equipment. the DSP56720/dsp56721 devices excel at audio processing for automotive and consumer audio applications requiring high mips. higher mips and memory requirements are driven by the new high-definition audio standards (dolby digital+, dolby truehd, dts-hd, for example) and the desire to process multiple audio streams. in addition, DSP56720/dsp56721 devices are optimal for the professional audio market requiring audio recording, signal processing, and digital audio synthesis. the DSP56720/dsp56721 processors provide a wealth of on-chip audio processing functions, via a plug and play software architecture system that supports audio decoding algorithms, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, among others. the DSP56720/dsp56721 devices also support various matrix decoders and sound field processing algorithms. with two dsp56300 cores, a single DSP56720 or dsp56721 device can replace dual-dsp de signs, saving costs while meeting high mips requirements. legacy peripherals from the previous dsp5636x/7x familie s are included, as well as a variety of new modules. included among the new modules are an asynchronous sample rate converter (asrc), inter-core communication (icc), an exte rnal memory controller (emc) to support sdram, and a sony/philips digital interface (s/pdif). the DSP56720/dsp56721 offer 200 million instructions per second (mips) per core using an internal 200 mhz clock. the DSP56720/dsp56721 are high density cmos devices with 3.3 v inputs and outputs. the DSP56720 device is slightly different than the dsp56721 device?the DSP56720 includes an external memory interface while the dsp56721 device does not. the DSP56720 block diagram is shown in figure 1 ; the dsp56721 block diagram is shown in figure 2 . symphony tm DSP56720 / dsp56721 multi-core audio processors
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 2 table of contents 1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 pinout for DSP56720 144-pin plastic lqfp package . .4 1.2 pinout for dsp56721 80-pin plastic lqfp package . . .6 1.3 pinout for dsp56721 144-pin plastic lqfp package . .7 1.4 pin multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1 chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . .8 2.1.2 thermal characteristics. . . . . . . . . . . . . . . . . . .10 2.1.3 power requirements . . . . . . . . . . . . . . . . . . . . .10 2.1.4 dc electrical characteristics . . . . . . . . . . . . . . .11 2.1.5 ac electrical characteristics . . . . . . . . . . . . . . .12 2.1.6 internal clocks . . . . . . . . . . . . . . . . . . . . . . . . .12 2.1.7 external clock operation. . . . . . . . . . . . . . . . . .13 2.1.8 reset, stop, mode select, and interrupt timing 14 2.2 module-level specifications . . . . . . . . . . . . . . . . . . . . .17 2.2.1 serial host interface (shi) spi protocol timing 18 2.2.2 serial host interface (shi) i 2 c protocol timing.24 2.2.3 programming the shi i 2 c serial clock . . . . . . 26 2.2.4 enhanced serial audio interface (esai) timing 27 2.2.5 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.6 gpio timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.7 jtag timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.8 watchdog timer timing . . . . . . . . . . . . . . . . . . 35 2.2.9 host data interface (hdi24) timing . . . . . . . . . 35 2.2.10 s/pdif timing . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.2.11 emc timing (DSP56720 only) . . . . . . . . . . . . . 43 3 functional description and application information . . . . . . . 48 4 hardware design considerations . . . . . . . . . . . . . . . . . . . . . 48 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 80-pin package outline drawing . . . . . . . . . . . . . . . . . 48 6.2 144-pin package outline drawing . . . . . . . . . . . . . . . . 51 7 product documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 3 figure 1. DSP56720 block diagram figure 2. dsp56721 block diagram shi tec esai esai_1 wdt gpio shi_1 tec_1 esai_2 esai_3 wdt_1 gpio pcu / agu / alu dma once once pcu / agu / alu dma on-chip memory p x y on-chip memory p x y dsp core-0 emc s/pdif gpio asrc arbiter 8 arbiters 0?7 2 jtags shared memory 8k blocks 0?7 (64k total) moda1, modb1, modc1, modd1 moda0, modb0, modc0, modd0 jtag extal/xtal dsp core-1 chip config arbiter 9 cgm shared bus 0 shared bus 1 shi timer esai esai_1 wdt gpio hdi24 shi_1 timer_1 esai_2 esai_3 wdt_1 gpio hdi24_1 pcu / agu / alu dma once once pcu / agu / alu dma on-chip memory p x y on-chip memory p x y dsp core-0 spdif gpio asrc arbiter 8 arbiters 0?7 2 jtags shared memory 8k blocks 0?7 (64k total) moda1, modb1, modc1, modd1 moda0, modb0, modc0, modd0 jtag hdi24 extal/xtal dsp core-1 chip config cgm shared bus 0 shared bus 1
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 4 1 pin assignments DSP56720 devices are available in one package type; dsp56721 devices are available in two package types. for the pin assignments of a specific device in a specific package, please see sections 1.2 ? 1.1 . for more detailed information about signals, refer to the DSP56720/dsp56721 reference manual (DSP56720rm). 1.1 pinout for DSP56720 144-pi n plastic lqfp package for the pinout of the DSP56720 144-pin plastic lqfp package, see figure 3 . table 1. pin assignments by package device package see DSP56720 144-pin plastic lqfp figure 3 on page 5 dsp56721 80-pin plastic lqfp figure 4 on page 6 144-pin plastic lqfp figure 5 on page 7
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 5 figure 3. DSP56720 144-pin package pinout 108 io_gnd 107 io_vdd 106 wdt 105 pinit/nmi 104 tdo 103 tdi 102 tck 101 tms 100 sdo2_1/sdi3_1 99 sdo3_1/sdi2_1 98 sdo4_1/sdi1_1 97 sdo5_1/sdi0_1 96 core_gnd 95 core_vdd 94 fsr 93 sckr 92 hckr 91 sckt 90 fst 89 hckt 88 sdo2/sdi3 87 sdo3/sdi2 86 sdo4/sdi1 85 sdo5/sdi0 84 spdifout1 83 spdifin1 82 io_gnd 81 io_vdd 80 extal 79 xtal 78 pllp_gnd 77 plld_gnd 76 plld_vdd 75 plla_gnd 74 plla_vdd 73 pllp_vdd lsync_in 37 lsync_out 38 lad23 39 lad22 40 lad21 41 lad20 42 lad19 43 lad18 44 lad17 45 core_vdd 46 core_gnd 47 io_vdd 48 io_gnd 49 lad16 50 lad15 51 lad14 52 lad13 53 lad12 54 lad11 55 lad10 56 lad9 57 io_vdd 58 io_gnd 59 core_vdd 60 core_gnd 61 lad8 62 lad7 63 lad6 64 lad5 65 lad4 66 lad3 67 lad2 68 lad1 69 lad0 70 io_gnd 71 io_vdd 72 core_vdd 1 core_gnd 2 lale 3 lcs0 4 lcs1 5 lcs2 6 lcs3 7 lcs4 8 lcs5 9 lcs6 10 lcs7 11 io_vdd 12 io_gnd 13 core_vdd 14 core_gnd 15 lwe 16 loe 17 lgpl5 18 lsda10 19 lcke 20 lclk 21 lbctl 22 lsdwe 23 lsdcas 24 lgta 25 la0 26 la1 27 la2 28 io_vdd 29 io_gnd 30 pllp1_gnd 31 pllp1_vdd 32 plld1_gnd 33 plld1_vdd 34 plla1_gnd 35 plla1_vdd 36 144 scan 143 moda0/irqa 142 modb0/irqb 141 modc0/plock 140 modd0/pg1 139 fsr_3 138 sckr_3 137 hckr_3 136 sckt_3 135 fst_3 134 hckt_3 133 io_gnd 132 io_vdd 131 core_gnd 130 core_vdd 129 moda1/irqc 128 modb1/irqd 127 modc1/nmi_1 126 modd1/pg2 125 sdo2_2/sdi3_2 124 sdo3_2/sdi2_2 123 sdo4_2/sdi1_2 122 sdo5_2/sdi0_2 121 sdo2_3/sdi3_3 120 sdo3_3/sdi2_3 119 sdo4_3/sdi1_3 118 sdo5_3/sdi0_3 117 ss /ha2 116 hreq /ph4 115 sck/scl 114 mosi/ha0 113 miso/sda 112 ss_1 /ha2_1 111 reset 110 core_gnd 109 core_vdd DSP56720 144-pin
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 6 1.2 pinout for dsp56721 80-pi n plastic lqfp package for the pinout of the dsp56721 80-pin plastic lqfp package, see figure 4 . figure 4. dsp56721 80-pin package 60 wdt 59 pinit/nmi 58 tdo 57 tdi 56 tck 55 tms 54 core_gnd 53 core_vdd 52 sdo4/sdi1 51 sdo5/sdi0 50 io_gnd 49 io_vdd 48 extal 47 xtal 46 pllp_gnd 45 plld_gnd 44 plld_vdd 43 plla_gnd 42 plla_vdd 41 pllp_vdd fst_3 21 hckt_3 22 sdo2_1/sdi3_1 23 sdo3_1/sdi2_1 24 core_vdd 25 core_gnd 26 sdo4_1/sdi1_1 27 sdo5_1/sdi0_1 28 fsr 29 sckr 30 hckr 31 sckt 32 io_vdd 33 io_gnd 34 core_vdd 35 core_gnd 36 fst 37 hckt 38 sdo2/sdi3 39 sdo3/sdi2 40 sdo2_3/sdi3_3 1 sdo3_3/sdi2_3 2 sdo4_3/sdi1_3 3 sdo5_3/sdi0_3 4 io_vdd 5 io_gnd 6 core_vdd 7 core_gnd 8 spdifin1 / sdo2_2/sdi3_2 9 spdifout1/sdo3_2/sdi2_2 10 sdo4_2/sdi1_2 11 sdo5_2/sdi0_2 12 fsr_3 13 sckr_3 14 sckt_3 15 gnd 16 gnd 17 gnd 18 gnd 19 gnd 20 80 scan 79 moda0/irqa 78 modb0/irqb 77 modc0/plock 76 io_gnd 75 io_vdd 74 core_gnd 73 core_vdd 72 moda1/irqc 71 modb1/irqd 70 modc1/nmi_1 69 ss /ha2 68 hreq /ph4 67 sck/scl 66 mosi/ha0 65 miso/sda 64 ss_1 /ha2_1 63 reset 62 core_gnd 61 core_vdd dsp56721 80-pin
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 7 1.3 pinout for dsp56721 144-pi n plastic lqfp package for the pinout of the dsp56721 144-pin plastic lqfp package, see figure 5 . figure 5. dsp56721 144-pin package pinout 1.4 pin multiplexing many pins are multiplexed. for more about pin multiplexing, refer to the DSP56720/dsp56721 reference manual (DSP56720rm). 108 io_gnd 107 io_vdd 106 wdt 105 piint/nmi 104 tdo 103 tdi 102 tck 101 tms 100 sckr_1 99 fsr_1 98 sckt_1 97 fst_1 96 sdo0_1 95 sdo1_1 94 io_gnd 93 io_vdd 92 core_gnd 91 core_vdd 90 sdo0 89 sdo1 88 sdo4/sdi1 87 sdo5/sdi0 86 spdifout1/h12/had12 85 spdifin1/h8/had8 84 hack/hrrq 83 horeq/htrq 82 io_gnd 81 io_vdd 80 extal 79 xtal 78 pllp_gnd 77 plld_gnd 76 plld_vdd 75 plla_gnd 74 plla_vdd 73 pllp_vdd has/ha0 37 ha1/ha8 38 ha2/ha9 38 hrw/hrd 40 hds/hwr 41 hcs/ha10 42 io_vdd 43 io_gnd 44 fst_3 45 hckt_3 46 sdo2_1/sdi3_1 47 sdo3_1/sdi2_1 48 core_vdd 49 core_gnd 50 sdo4_1/sdi1_1 51 sdo5_1/sdi0_1 52 fsr 53 sckr 54 hckr 55 sckt 56 io_vdd 57 io_gnd 58 core_vdd 59 core_gnd 60 fst 61 hckt 62 sdo2/sdi3 63 sdo3/sdi2 64 io_gnd 65 io_vdd 66 h0/had0 67 h1/had1 68 h2/had2 69 h3/had3 70 h4/had4 71 h5/had5 72 tio0/h15/had15 1 pg18/hdi_sel 2 io_gnd 3 tio0_1/h18/had18 4 core_vdd 5 core_gnd 6 sdo2_3/sdi3_3 7 sdo3_3/sdi2_3 8 sdo4_3/sdi1_3 9 sdo5_3/sdi0_3 10 io_vdd 11 io_gnd 12 core_vdd 13 core_gnd 14 sdo2_2/sdi3_2 15 sdo3_2/sdi2_2 16 sdo4_2/sdi1_2 17 sdo5_2/sdi0_2 18 hckr_3 19 fsr_3 20 sckr_3 21 sckt_3 22 io_vdd 23 io_gnd 24 h6/had6 25 h7/had7 26 spdifin2/h9/had9 27 spdifin3/h10/had10 28 spdifin4/h11/had11 29 spdifout2/h13/had13 30 splock/h14/had14 31 gnd 32 gnd 33 gnd 34 gnd 35 gnd 36 144 scan 143 moda0/irqa 142 modb0/irqb 141 modc0/plock 140 modd0/pg1 139 io_gnd 138 io_vdd 137 core_gnd 136 core_vdd 135 moda1/irqc 134 modb1/irqd 133 modc1/nmi_1 132 modd1/pg2 131 fsr_2 130 sckr_2 129 sckt_2 128 fst_2 127 sdo0_2 126 sdo1_2 125 io_gnd 124 io_vdd 123 sdo0_3 122 sdo1_3 121 ss /ha2 120 hreq /ph4 119 sck/scl 118 mosi/ha0 117 miso/sda 116 ss_1 /ha2_1 115 hreq_1 /ph4_1 114 sck_1/scl_1 113 mosi_1/ha0_1 112 miso_1/sda_1 111 reset 110 core_gnd 109 core_vdd dsp56721 144-pin
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 8 2 electrical characteristics for electrical characteristics, see table 2 . 2.1 chip-level conditions for a summary of chip-level conditions in this section, see table 3 . 2.1.1 maximum ratings for maximum ratings, see table 4 . caution this device contains circuitry protecting against damage due to high static voltage or electrical fields. however, normal precauti ons should be taken to avoid exceeding maximum voltage ratings. reliability of operatio n is enhanced if unused inputs are pulled to an appropriate logic voltage le vel (for example, either gnd or v dd ). the suggested value for a pull-up or pull-down resistor is 4.7 k . note in the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another sp ecification does not yield a reasonable sum. a maximum specification is calculated using a worst case va riation of process parameter values in one direction. the minimum speci fication is calculated using the worst case for the same parameters in the opposite direction. therefor e, a ?maximum? value fo r a specification will never occur in the same device that has a ?minimum? value for a nother specification; adding a maximum to a minimum represents a condition that can never exist. table 2. electrical characteristics for see section 2.1, ?chip-level conditions ? on page 8 section 2.2, ?module-level specifications ? on page 17 table 3. chip-level conditions for see section 2.1.1, ?maximum ratings ? on page 8 section 2.1.2, ?thermal characteristics ? on page 10 section 2.1.3, ?power requirements ? on page 10 section 2.1.4, ?dc electrical characteristics ? on page 11 section 2.1.5, ?ac electrical characteristics ? on page 12 section 2.1.6, ?internal clocks ? on page 12 section 2.1.7, ?external clock operation ? on page 13 section 2.1.8, ?reset, stop, mode select, and interrupt timing ? on page 14
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 9 table 4. maximum ratings rating 1 symbol value 1, 2 unit supply voltage v core_vdd, v plld_vdd -0.3 to + 1.26 v v pllp_vdd, v io_vdd, v plla_vdd , -0.3 to + 4.0 v maximum core_vdd power supply ramp time 4 tr 1 0 m s input voltage per pin excluding vdd and gnd v in gnd -0.3 to 5.5v v current drain per pin excluding v dd and gnd (except for pads listed below) i12ma lsync_out i lsync_out 16 ma lclk i lclk 16 ma lale i ale 16 ma tdo i jtag 24 ma operating temperature range 3 t j -40 to +125 c storage temperature t stg -65 to +150 c esd protected voltage (human body model) ? 2000 v esd protected voltage (charged device) ? all pins ? corner pins ? 500 750 v notes: 1. gnd = 0 v, t j = -40c to 125c, cl = 50pf 2. absolute maximum ratings are stress rati ngs only, and functional operation at the maximum is not guaranteed. stress beyond th e maximum rating may affect device reliability or cause permanent damage to the device. 3. operating temperature qualifi ed for consumer applications. t j = t a + q ja x power. variables used were core current = 900ma, i/o current = 200ma, core voltage = 1.1 v, i/o voltage = 3.6 v, t a = 105c. 4. if the power supply ramp to full supply time is longer than 10 ms, the por circuitry will not operate correctly, causing erro neous operation.
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 10 2.1.2 thermal characteristics for thermal characteristics, see table 5 . 2.1.3 power requirements to prevent high current conditions due to possible improper seque ncing of the power supplies, use an external schottky diode as shown in figure 6 , connected between the DSP56720/dsp56721 io_vdd and core_vdd power pins. figure 6. prevent high current conditions by using external schottky diode if an external schottky diode is not used (to prevent a high current condition at powe r-up), then io_vdd must be applied ahead of core_vdd, as shown in figure 7 . figure 7. prevent high current conditions by applying io_vdd before core_vdd for correct operation of the internal power-on reset logic, the core_vdd ramp rate (tr) to full supply must be less than 10 ms, as shown in figure 8 . table 5. thermal characteristics characteristic board type symbol lqfp values unit natural convection, junction-to-ambient thermal resistance 1,2 single layer board (1s) r ja or ja 57 for 80 qfp 49 for 144 qfp c/w four layer board (2s2p) 44 for 80 qfp 40 for 144 qfp c/w junction-to-case thermal resistance 3 ?r jc or jc 10 for 80 qfp 9 for 144 qfp c/w notes: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipat ion of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 3. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). io_vdd core_vdd external schottky diode core_vdd io_vdd
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 11 figure 8. ensure correct operation of power-on reset with fast ramp of core_vdd 2.1.4 dc electrical characteristics for dc electrical characteristics, see table 6 . table 6. dc electrical characteristics characteristics symbol min typ max unit supply voltages ? core (core_vdd) ? pll (plld_vdd, plld1_vdd) v dd 0.9 1.0 1.1 v supply voltages ? i/o (io_vdd) ? pll (pllp_vdd, pllp1_vdd) ? pll (plla_vdd, plla1_vdd) v ddio 3.14 3.3 3.46 v input high voltage v ih 2.0 ? v io_vdd+2v v note: to avoid a high current condition and possible system damage, all 3.3 volt supplies must rise before the 1.0 volt supplies rise. input low voltage v il -0.3 ? 0.8 v input leakage current i in ?? 84 a clock pin input capacitance (extal) c in 18 pf high impedance (off-state) input current (@ 3.3 v or 0v) i tsi -10 ? 10 a output high voltage i oh = -12 ma lsync_out, lale, lclk pins i oh = -16 ma, tdo pin i oh = -24 ma v oh 2.4 ? ? v output low voltage i ol = 12 ma lsync_out, lale, lclk pins i ol = 16 ma, tdo pins i ol = 24 ma v ol ?? 0.4v core_vdd tr must be < 10 ms 0 v 1.0v tr
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 12 2.1.5 ac electrical characteristics the timing waveforms shown in the ac electrical characteristics section are tested with a v il maximum of 0.8 v and a v ih minimum of 2.0 v for all pins. ac timing specifications, which are referenced to a device i nput signal, are measured in production with respect to the 50% point of the respective in put signal?s transition. DSP56720/dsp56721 output levels are measured with the production test machine v ol and v oh reference levels set at 0.4 v and 2.4 v, respectively. 2.1.6 internal clocks internal clock characteristics are listed in table 7 . internal supply current 1 (core only) at internal clock of 200 mhz ? in normal mode i cci ? 190 780 ma ? in wait mode i ccw ? 90 680 ma ? in stop mode 2 i ccs ? 50 640 ma input capacitance c in ?? 10pf notes: 1. the current consumption section provides a formula to comput e the estimated current requirements in normal mode. in order to obtain these results, all inputs must be terminated (i.e., not allowed to float). measurem ents are based on synthetic intens ive dsp benchmarks. the power consumption numbers in this specific ation are 90% of the measured results of this benchmark. this reflects typical dsp applications. typical in ternal supply current is measured with v core_vdd = 1.0v, v dd_io = 3.3v at t j = 25c. maximum internal supply current is measured with v core_vdd = 1.10v, v io_vdd) = 3.6v at t j = 125c. 2. in order to obtain these results, all inputs, which are not disconnected at stop mode, must be terminated (i.e., not allowed to float). table 7. internal clocks no. characteristics symbol min typ max unit condition 1 comparison frequency fref 2 ? 8 mhz fref = fin/nr 2 input clock frequency fin max = 200 mhz 3 pll vco frequency fvco 200 ? 400 mhz fvco = (fin * nf)/nr 4 output clock frequency [1] ? with pll enabled ? with pll disabled fout 25 ? ? 200 200 mhz fout= fvco/no fout = fin 5 duty cycle ? 40 50 60 % fvco= 200 mhz ? 400 mhz notes: fin = external frequency, nf = multiplication fa ctor, nr = predivision factor, no = output divider table 6. dc electrical characteristics (continued) characteristics symbol min typ max unit
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 13 2.1.7 external clock operation the DSP56720/dsp56721 system clock is derived from the on-chip oscillator or is externally supplied. to use the on-chip oscillator, connect a crystal and associ ated resistor/capacitor co mponents to extal and xtal; see the example in figure 9 . figure 9. using the on-chip oscillator if the DSP56720/dsp56721 system clock is an externally s upplied square wave voltage source, it is connected to extal ( figure 10 ). when the external square wave source is c onnected to extal, the xtal pin is not used. figure 10. external clock timing table 8. clock operation no. characteristics symbol min max units 1 extal input high 1 (40% to 60% duty cycle) ? crystal oscillator ? square wave input eth 16.67 2.5 100 inf ns xtal extal suggested component values: fosc = 24.576 mhz r = 1 m 10% c (extal)= 18 pf calculations are for a 5 ? 30 mhz crystal with the following parameters: ? shunt capacitance (c 0 ) of 10 pf ? 12 pf ? series resistance 40 ohm c (xtal) = 18 pf ? drive level of 10 w r xtal1 c c extal v il v ih midpoint note: the midpoint is 0.5 (v ih + v il ). eth etl etc 2 3 1
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 14 2.1.8 reset, stop, mode se lect, and interrupt timing for reset, stop, mode select, and interrupt timing, see table 9 . 2 extal input low 1 (40% to 60% duty cycle) ? crystal oscillator ? square wave input etl 16.67 2.5 100 inf ns 3 extal cycle time ? with pll disabled ? with pll enabled etc 5 33.3 inf 500 ns 4 instruction cycle time ? with pll disabled ? with pll enabled tc 5.00 5.00 inf 5120 ns notes: 1. measured at 50% of the input transition. 2. the indicated duty cycle is for the specified maximum frequency for which a part is rated. the minimum clock high or low time required for correct operation, howeve r, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the si gnal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 3. a valid clock signal must be applied to the extal pin within 3 ms of the DSP56720/dsp56721 being powered up. table 9. reset, stop, mode select, and interrupt timing parameters no. characteristics expression min max unit 10 delay from reset assertion to all pins at reset value 3 ? ? 11 ns 11 required reset duration 4 ? power on, external clock generator, pll disabled ? power on, external clock generator, pll enabled 2 x t c 2 x t c 10 10 ? ? ns ns 13 syn reset deassert delay time ? minimum 2 t c 10 ? ns ? maximum (pll enabled) (2 x t c )+t lock 200 ? us 14 mode select setup time ? 10.0 ? ns 15 mode select hold time ? 10.0 ? ns 16 minimum edge-triggered interrupt request assertion width ? 4 ? ns 17 minimum edge-triggered interrupt request deassertion width ? 4 ? ns 18 delay from interrupt trigger to interrupt code execution 10 t c + 4 54 ? ns table 8. clock operation (continued) no. characteristics symbol min max units
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 15 19 duration of level sensitive irqa assertion to ensure interrupt service (when exiting stop) 1, 2, 3 ? pll is active during stop and stop delay is enabled (omr bit 6 = 0) ( 128k t c) 655 ? s ? pll is active during stop and stop delay is not enabled (omr bit 6 = 1) 25 t c 125 ? ns ? pll is not active during stop and stop delay is enabled (omr bit 6 = 0) (128k x t c ) + t lock 855 ? s ? pll is not active during stop and stop delay is not enabled (omr bit 6 = 1) (25 x t c ) + t lock 200 ? s 20 ? delay from irqa , irqb , irqc , irqd , nmi assertion to general-purpose transfer output valid caused by first interrupt instruction execution 1 10 x t c + 3.8 ? 53.8 ns 21 interrupt requests rate 1 ? esai, esai_1, esai_2, esai_3, shi, shi_1, timer, timer_1 12 x t c ?60.0ns ? dma 8 x t c ?40.0ns ?irq , nmi (edge trigger) 8 x t c ?40.0ns ?irq (level trigger) 12 x t c ?60.0ns 22 dma requests rate ? data read from esai, esai_1, esai _2, esai_3, shi, shi_1 6 x t c ?30.0ns ? data write to esai, esai_1, esai _2, esai_3, shi, shi_1 7 x t c ?35.0ns ? timer, timer_1 2 x t c ?10.0ns ?irq , nmi (edge trigger) 3 x t c ?15.0ns notes: 1. when using fast interrupts and when irqa , irqb , irqc , and irqd are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. to avoid these timing re strictions, the edge-triggered mode is recommended when using fast interrupts. long interrupts are recomm ended when using level-sensitive mode. 2. for pll disable, if using an external clock (pctl bit 13 = 1) , no stabilization delay is required and recovery time will be d efined by the omr bit 6 settings. for pll enable, (if bit 12 of the pctl register is 0), the pll is shut down during stop. recovering from stop requires the pll to get locked. the pll lock procedure duration, pll lock cycles (plc), may be in the range of 200 s. 3. periodically sampled and not 100% tested. 4. reset duration is measured during the time in which reset is asserted, v dd is valid, and the extal input is active and valid. when v dd is valid, but the other ?required reset duration? conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant po wer consumption and heat-up. designs should minimize this state t o the shortest possible duration. table 9. reset, stop, mode select, and interrupt timing parameters no. characteristics expression min max unit
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 16 figure 11. reset timing diagram figure 12. external fast interrupt timing diagram v ih reset all pins 10 11 13 reset value a) first interrupt instruction execution general purpose i/o irqa , irqb , irqc , irqd , nmi, nmi_1 b) general purpose i/o irqa , irqb , irqc , irqd , nmi, nmi_1 18 19 20
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 17 figure 13. external interrupt timing diagram (negative edge-triggered) figure 14. mode select set-up and hold timing diagram 2.2 module-level specifications for a summary of the module-level sp ecifications in this section, see table 10 . table 10. module-level specifications for see section 2.2.1, ?serial host interface (shi) spi protocol timing ? on page 18 section 2.2.2, ?serial host interface (shi) i 2 c protocol timing ? on page 24 section 2.2.3, ?progr amming the shi i 2 c serial clock ? on page 26 section 2.2.4, ?enhanced serial audio interface (esai) timing ? on page 27 section 2.2.5, ?timer timing ? on page 32 section 2.2.6, ?gpio timing ? on page 32 section 2.2.7, ?jtag timing ? on page 33 section 2.2.8, ?watchdog timer timing ? on page 35 section 2.2.9, ?host data interface (hdi24) timing ? on page 35 section 2.2.10, ?s/pdif timing ? on page 42 section 2.2.11, ?emc timing (DSP56720 only) ? on page 43 irqa , irqb , irqc, irqd , nmi, nmi_1 irqa , irqb , irqc, irqd , nmi, nmi_1 16 17 reset moda, modb, modc, modd, pinit v ih irqa , irqb , irqc ,irqd , nmi v ih v ih 14 15 v il v il
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 18 2.2.1 serial host interface (shi) spi protocol timing see table 11 for shi spi protocol timing parameters and figure 15 , figure 16 , figure 17 , and figure 18 for timing diagrams. table 11. serial host interface spi protocol timing parameters no. characteristics 1,3,4 mode filter mode expression min max unit 23 minimum serial clock cycle = t spicc (min) master/slave bypassed 10 x t c + 9 59.0 ? ns very narrow 10 x t c + 9 59.0 ? ns narrow 10 x t c + 133 183.0 ? ns wide 10 x t c + 333 373.0 ? ns xx tolerable spike width on data or clock in ? bypassed ? ? 0 ns very narrow ? ? 10 ns narrow ? ? 50 ns wide ? ? 100 ns 24 serial clock high period master bypassed 0.5 x (t spicc - 10) 33.0 ? ns very narrow 0.5 x (t spicc - 10) 33.0 ? ns narrow 0.5 x (t spicc - 10) 86.0 ? ns wide 0.5 x (t spicc - 10) 121.5 ? ns slave bypassed 2.5 x t c + 12 22.5 ? ns very narrow 2.5 x t c + 12 22.5 ? ns narrow 2.5 x t c + 102 114.5 ? ns wide 2.5 x t c + 189 201.5 ? ns 25 serial clock low period master bypassed 0.5 x (t spicc - 10) 33.0 ? ns very narrow 0.5 x (t spicc - 10) 33.0 ? ns narrow 0.5 x (t spicc - 10) 86.0 ? ns wide 0.5 x (t spicc - 10) 121.5 ? ns slave bypassed 2.5 x t c + 12 22.5 ? ns very narrow 2.5 x t c + 12 22.5 ? ns narrow 2.5 x t c + 102 114.5 ? ns wide 2.5 x t c + 189 201.5 ? ns 26 serial clock rise/fall time master slave ? ? ? ? ? ? ? 5 ns ns
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 19 27 ss assertion to first sck edge cpha = 0 slave bypassed 3.5 x t c +15 32.5 ? ns very narrow 3.5 x t c +5 22.5 ? ns narrow ? 0 ? ns wide ? 0 ? ns cpha = 1 slave bypassed ? 10 ? ns very narrow ? 0 ? ns narrow ? 0 ? ns wide ? 0 ? ns 28 last sck edge to ss not asserted slave bypassed ? 12 ? ns very narrow ? 22 ? ns narrow ? 100 ? ns wide ? 200 ? ns 29 data input valid to sck edge (data input set-up time) master /slave bypassed ? 0 ? ns very narrow ? 0 ? ns narrow ? 0 ? ns wide ? 0 ? ns 30 sck last sampling edge to data input not valid master /slave bypassed 2 x t c + 10 10 ? ns very narrow 2 x t c + 30 40 ? ns narrow 2 x t c + 60 70 ? ns wide ? 100.0 ? ns 31 ss assertion to data out active slave ? ? 5 ? ns 32 ss deassertion to data high impedance 2 slave ? ? ? 9 ns 33 sck edge to data out valid (data out delay time) master /slave bypassed ? ? 46.2 ns very narrow ? ? 270 ns narrow ? ? 376 ns wide ? ? 521 ns 34 sck edge to data out not valid (data out hold time) master /slave bypassed ? 11.67 ? ns very narrow ? 15 ? ns narrow ? 55 ? ns wide ? 105 ? ns 35 ss assertion to data out valid (cpha = 0) slave ? ? ? 14.0 ns table 11. serial host interface spi protocol timing parameters (continued) no. characteristics 1,3,4 mode filter mode expression min max unit
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 20 36 first sck sampling edge to hreq output deassertion slave bypassed ? 45 ? ns very narrow ? 55 ? ns narrow ? 95 ? ns wide ? 145 ? ns 37 last sck sampling edge to hreq output not deasserted (cpha = 1) slave bypassed ? 50.0 ? ns very narrow ? 60.0 ? ns narrow ? 100.0 ? ns wide ? 150.0 ? ns 38 ss deassertion to hreq output not deasserted (cpha = 0) slave ? ? 45.0 ? ns 39 ss deassertion pulse width (cpha = 0) slave ? t c + 6 11.0 ? ns 40 hreq in assertion to first sck edge master ? 0.5 x t spicc + 3.0 x t c + 43 96.0 ? ns 41 hreq in deassertion to last sck sampling edge (hreq in set-up time) (cpha = 1) master ? ? 0 ? ns 42 first sck edge to hreq in not asserted (hreq in hold time) master ? ? 0 ? ns 43 hreq assertion width master ? 3.0 x t c 15 ? ns notes: 1. v core_vdd = 1.0 0.10 v; t j = -40c to 125c; c l = 50 pf. 2. periodically sampled, not 100% tested. 3. all times assume noise free inputs. 4. all times assume internal clock frequency of 200 mhz. 5. shi_1 specs match those of shi. table 11. serial host interface spi protocol timing parameters (continued) no. characteristics 1,3,4 mode filter mode expression min max unit
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 21 figure 15. spi master timing diagram (cpha = 0) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) hreq (input) 23 24 25 26 26 23 26 26 25 24 29 30 30 29 33 34 42 40 43 msb lsb lsb valid msb valid
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 22 figure 16. spi master timing diagram (cpha = 1) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) hreq (input) 23 24 25 26 26 23 26 26 25 24 29 29 30 33 34 42 40 41 30 43 msb lsb msb valid lsb valid
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 23 figure 17. spi slave timing diagram (cpha = 0) ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) hreq (output) 23 24 25 26 26 23 26 26 25 24 35 31 33 34 29 30 38 36 34 32 29 30 28 39 27 lsb msb msb valid lsb valid
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 24 figure 18. spi slave timing diagram (cpha = 1) 2.2.2 serial host interface (shi) i 2 c protocol timing see table 12 for shi i 2 c protocol timing parameters and figure 19 for the timing diagram. table 12. shi i 2 c protocol timing parameters standard i 2 c no. characteristics 1,2,3,4,5 symbol/ expression standard fast-mode unit min max min max tolerable spike width on scl or sda filters bypassed very narrow filters enabled narrow filters enabled wide filters enabled. ? ? ? ? ? 0 10 50 100 ? ? ? ? 0 10 50 100 ns ns ns ns 44 scl clock frequency f scl ? 100 ? 400 khz 44 scl clock cycle t scl 10 ? 2.5 ? s 45 bus free time t buf 4.7 ? 1.3 ? s 46 start condition set-up time t susta 4.7 ? 0.6 ? s ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) hreq (output) 23 24 25 26 26 26 26 25 24 31 33 29 30 37 34 32 29 28 27 33 30 36 msb lsb msb valid lsb valid
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 25 47 start condition hold time t hd;sta 4.0 ? 0.6 ? s 48 scl low period t low 4.7 ? 1.3 ? s 49 scl high period t high 4.0 ? 1.3 ? s 50 scl and sda rise time t r ? 5.0 ? 5.0 ns 51 scl and sda fall time t f ? 5.0 ? 5.0 ns 52 data set-up time t su;dat 250 ? 100 ? ns 53 data hold time t hd;dat 0.0 ? 0.0 0.9 s 54 dsp clock frequency ? filters bypassed ? very narrow filters enabled ? narrow filters enabled ? wide filters enabled f osc 10.6 10.6 11.8 13.1 ? ? ? ? 28.5 28.5 39.7 61.0 ? ? ? ? mhz mhz mhz mhz 55 scl low to data out valid t vd;dat ? 3.4 ? 0.9 s 56 stop condition setup time t su;sto 4.0 ? 0.6 ? s 57 hreq in deassertion to last scl edge (hreq in set-up time) t su;rqi 0.0 ? 0.0 ? ns 58 first scl sampling edge to hreq output deassertion 2 ? filters bypassed ? very narrow filters enabled ? narrow filters enabled ? wide filters enabled t ng;rqo 4 t c + 30 4 t c + 50 4 t c + 130 4 t c + 230 ? ? ? ? 50.0 70.0 250.0 150.0 ? ? ? ? 50.0 70.0 150.0 250.0 ns ns ns ns 59 last scl edge to hreq output not deasserted 2 ? filters bypassed ? very narrow filters enabled ? narrow filters enabled ? wide filters enabled t as;rqo 2 t c + 30 2 t c + 40 2 t c + 80 2 t c + 130 40 50 90 140 ? ? ? ? 40 50 90 140 ? ? ? ? ns ns ns ns 60 hreq in assertion to first scl edge ? filters bypassed ? very narrow filters enabled ? narrow filters enabled ? wide filters enabled t as;rqi 4327 4317 4282 4227 ? ? ? ? 927 917 877 827 ? ? ? ? ns ns ns ns 61 first scl edge to hreq is not asserted (hreq in hold time.) t ho;rqi 0.0 ? 0.0 ? ns notes: 1. v core_vdd = 1.00 0.10 v; t j = -40c to 125c; c l = 50 pf. 2. pull-up resistor: r p (min) = 1.5k ohms. 3. capacitive load: c b (max) = 50 pf. 4. all times assume noise free inputs. 5. all times assume internal clock frequency of 200 mhz. 6. shi_1 specs match those of shi. table 12. shi i 2 c protocol timing parameters (continued) standard i 2 c no. characteristics 1,2,3,4,5 symbol/ expression standard fast-mode unit min max min max
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 26 2.2.3 programming the shi i 2 c serial clock the programmed serial clock cycle, t i 2 ccp , is specified by the value of the hdm[7:0 ] and hrs bits of the hckr (shi clock control register). the expression for t i 2 ccp is t i 2 ccp = [t c 2 (hdm[7:0] + 1) (7 (1 ? hrs) + 1)] eqn. 1 where ? hrs is the pre scaler rate select bit. when hrs is cleared, the fixed divide-by-eight pre scaler is operational. wh en hrs is set, the pre scaler is bypassed. ? hdm[7:0] are the divider modulus select bits. a divide ratio from 1 to 256 (hdm[7:0] = $00 to $ff) may be selected. in i 2 c mode, the user may select a value for the programmed seri al clock cycle from 6 t c (if hdm[7:0] = $02 and hrs = 1) eqn. 2 to 4096 t c (if hdm[7:0] = $ff and hrs = 0) eqn. 3 the programmed serial clock cycle (t i 2 ccp ) should be chosen in order to achieve the desired scl serial clock cycle (t scl ), as shown in equation 4. t i 2 ccp + 3 t c + 45ns + t r (nominal, scl serial clock cycle (tscl) generated as master) eqn. 4 figure 19. i 2 c timing diagram 44 46 49 48 50 51 53 52 45 58 55 56 61 47 60 57 59 scl sda hreq stop start msb lsb ack stop
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 27 2.2.4 enhanced serial audio interface (esai) timing see table 13 for esai timing parameters and figure 20 , figure 21 , figure 22 , and figure 23 for timing diagrams. table 13. enhanced serial audi o interface timing parameters no. characteristics 1, 3, 4 symbol expression 5 min max condition 2 unit 62 clock cycle 5 t ssicc 4 t c 4 t c 20.0 20.0 ? ? i ck i ck ns 63 clock high period ? for internal clock ? 2 t c 10 ? ? ns ? for external clock 2 t c 10 ? ? 64 clock low period ? for internal clock ? 2 t c 10 ? ? ns ? for external clock 2 t c 10 ? ? 65 sckr rising edge to fsr out (bl) high ? ? ? ? 17.0 7.0 x ck i ck a ns 66 sckr rising edge to fsr out (bl) low ? ? ? ? 17.0 7.0 x ck i ck a ns 67 sckr rising edge to fsr out (wr) high 6 ??? ? 19.0 9.0 x ck i ck a ns 68 sckr rising edge to fsr out (wr) low 6 ??? ? 19.0 9.0 x ck i ck a ns 69 sckr rising edge to fsr out (wl) high ? ? ? ? 16.0 6.0 x ck i ck a ns 70 sckr rising edge to fsr out (wl) low ? ? ? ? 17.0 7.0 x ck i ck a ns 71 data in setup time before sckr (sck in synchronous mode) falling edge ??12.0 19.0 ? ? x ck i ck ns 72 data in hold time after sckr falling edge ? ? 3.5 9.0 ? ? x ck i ck ns 73 fsr input (bl, wr) high before sckr falling edge 6 ??2.0 12.0 ? ? x ck i ck a ns 74 fsr input (wl) high before sckr falling edge ? ? 2.0 12.0 ? ? x ck i ck a ns 75 fsr input hold time after sckr falling edge ? ? 2.5 8.5 ? ? x ck i ck a ns 76 flags input setup before sckr falling edge ? ? 0.0 19.0 ? ? x ck i ck s ns 77 flags input hold time after sckr falling edge ? ? 6.0 0.0 ? ? x ck i ck s ns 78 sckt rising edge to fst out (bl) high ? ? ? ? 18.0 8.0 x ck i ck ns 79 sckt rising edge to fst out (bl) low ? ? ? ? 20.0 10.0 x ck i ck ns
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 28 80 sckt rising edge to fst out (wr) high 6 ??? ? 20.0 10.0 x ck i ck ns 81 sckt rising edge to fst out (wr) low 6 ??? ? 22.0 12.0 x ck i ck ns 82 sckt rising edge to fst out (wl) high ? ? ? ? 19.0 9.0 x ck i ck ns 83 sckt rising edge to fst out (wl) low ? ? ? ? 20.0 10.0 x ck i ck ns 84 sckt rising edge to data out enable from high impedance ??? ? 22.0 17.0 x ck i ck ns 85 sckt rising edge to transmitter #0 drive enable assertion ??? ? 17.0 11.0 x ck i ck ns 86 sckt rising edge to data out valid ? ? ? ? 18.0 13.0 x ck i ck ns 87 sckt rising edge to data out high impedance 7 ??? ? 21.0 16.0 x ck i ck ns 88 sckt rising edge to transmitter #0 drive enable deassertion 7 ??? ? 14.0 9.0 x ck i ck ns 89 fst input (bl, wr) setup time before sckt falling edge 6 ??2.0 18.0 ? ? x ck i ck ns 90 fst input (wl) setup time before sckt falling edge ? ? 2.0 18.0 ? ? x ck i ck ns 91 fst input hold time after sckt falling edge ? ? 4.0 5.0 ? ? x ck i ck ns 92 fst input (wl) to data out en able from high impedance ? ? ? 21.0 ? ns 93 fst input (wl) to transmitter #0 drive enable assertion ? ? ? 14.0 ? ns 94 flag output valid after sckt rising edge ? ? ? ? 14.0 9.0 x ck i ck ns table 13. enhanced serial audio inte rface timing parameters (continued) no. characteristics 1, 3, 4 symbol expression 5 min max condition 2 unit
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 29 95 hckr/hckt clock cycle ? 2 x t c 10 ? ? ns 96 hckt input rising edge to sckt output ? ? ? 18.0 ? ns 97 hckr input rising edge to sckr output ? ? ? 18.0 ? ns notes: 1. v core_vdd = 1.00 0.10 v; t j = -40c to 125c; c l = 50 pf. 2. i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that sckt a nd sckr are two different clocks.) i ck s = internal clock, synchronous mode (synchronous implies that sckt and sckr are the same clock.) 3. bl = bit length wl = word length wr = word length relative 4. sckt(sckt pin) = transmit clock sckr(sckr pin) = receive clock fst(fst pin) = transmit frame sync fsr(fsr pin) = receive frame sync hckt(hckt pin) = transmit high frequency clock hckr(hckr pin) = receive high frequency clock 5. for the internal clock, the external clock cycle is defined by tc and the esai control register. 6. the word-relative frame sync signal waveform relative to the cl ock operates in the same manner as the bit-length frame sync s ignal waveform, but spreads from one serial clock before first bit cl ock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7. periodically sampled and not 100% tested. 8. esai_1, esai_2, esai_3 specs match those of esai. table 13. enhanced serial audio inte rface timing parameters (continued) no. characteristics 1, 3, 4 symbol expression 5 min max condition 2 unit
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 30 figure 20. esai transmitter timing diagram see note sckt (input/output) fst (bit) out fst (word) out data out transmitter #0 drive enable (internal signal) fst (bit) in fst (word) in flags out note: in network mode, output flag transitions can occu r at the start of each time slot within the frame. in normal mode, the output flag state is asserted for the entire frame period. 62 64 78 79 82 83 87 86 86 84 93 88 85 91 89 92 90 91 94 63 last bit first bit
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 31 figure 21. esai receiver timing diagram figure 22. esai hckt timing diagram sckr (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in 62 64 65 69 70 72 71 75 73 74 75 77 76 63 66 first bit last bit 96 95 hckt sckt (output)
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 32 figure 23. esai hckr timing 2.2.5 timer timing see table 14 for timer timing parameters and figure 24 for the timing diagram. figure 24. tio timer event i nput restrictions diagram 2.2.6 gpio timing see table 15 for general purpose input and output (gpio) timing and figure 25 for the timing diagram. table 14. timer timing parameters no. characteristics expression unit min max 98 tio low 2 t c + 2.0 12.0 ? ns 99 tio high 2 t c + 2.0 12.0 ? ns notes: 1. v core_vdd = 1.00 v 0.10 v; t j = -40c to 125c, c l = 50 pf 2. timer_1 specs match those of timer table 15. gpio timing parameters no. characteristics 1 expression min max unit 100 fsys edge to gpio out valid (gpio out delay time) 2 ??7ns 101 fsys edge to gpio out not valid (gpio out hold time) 2 ??7ns 102 fsys in valid to extal edge (gpio in set-up time) 2 ?2?ns 103 fsys edge to gpio in not valid (gpio in hold time) 2 ?0?ns 104 minimum gpio pulse high width 2 x tc 10 ? ns 97 95 hckr sckr (output) 99 98 tio
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 33 figure 25. gpio timing diagram 2.2.7 jtag timing see table 16 for joint test action group (jtag) timing parameters, and figure 26 , figure 27 , and figure 28 for timing diagrams. 105 minimum gpio pulse low width 2 x tc 10 ? ns 106 gpio out rise time ? ? 13.0 ns 107 gpio out fall time ? ? 13.0 ns notes: 1. v core_vdd = 1.0 v 0.10 v; t j = -40c to 125c; c l = 50 pf table 16. jtag timing parameters no. characteristics all frequencies unit min max 108 tck frequency of operation (1/(t c 3); maximum 10 mhz) ? 10.0 mhz 109 tck cycle time in crystal mode 100.0 ? ns 110 tck clock pulse width measured at 1.65 v 50.0 ? ns 111 tck rise and fall times ? 3.0 ns 112 boundary scan input data setup time 15.0 ? ns 113 boundary scan input data hold time 24.0 ? ns 114 tck low to output data valid ? 40.0 ns 115 tck low to output high impedance ? 40.0 ns table 15. gpio timing (continued)parameters no. characteristics 1 expression min max unit 100 101 102 103 104 105 106 107 fsys valid gpio (output) gpio input) gpio (output)
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 34 figure 26. test clock input timing diagram figure 27. debugger port timing diagram 116 tms, tdi data setup time 5.0 ? ns 117 tms, tdi data hold time 25.0 ? ns 118 tck low to tdo data valid ? 44.0 ns 119 tck low to tdo high impedance ? 44.0 ns notes: 1. v core_vdd = 1.0 v 0.10 v; t j = -40c to 125c , c l = 50 pf 2. all timings apply to once module data transfers because it uses the jtag port as an interface. table 16. jtag timing parameters (continued) no. characteristics all frequencies unit min max 109 110 110 111 111 tck (input) vil v m vih v m vih vil 113 112 114 115 114 tck (input) data inputs data outputs data outputs data outputs input data valid output data valid output data valid
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 35 figure 28. test access port timing diagram 2.2.8 watchdog timer timing for watchdog timer timing, see table 17 . 2.2.9 host data interface (hdi24) timing the hdi24 module is only on the dsp56721 device; the dsp56 720 device does not have a hdi24 module. also, only 16 bits of the hdi24 interface are pinned out on the dsp56721 device. see table 18 for hdi24 timing and figure 29 , figure 30 , figure 30 , figure 31 , figure 32 , figure 33 , figure 34 , and figure 35 for timing diagrams. table 17. watchdog timer timing parameters no. characteristics expression min max unit 120 delay from time-out to fall of wdt , wdt_1 2 t c 10.0 ? ns 121 delay from timer clear to rise of wdt , wdt_1 2 tc 10.0 ? ns table 18. hdi24 timing parameters no. characteristics 2 expression 200 mhz unit min max 317 read data strobe assertion width 3 hack read assertion width t c + 9.9 14.9 ? ns 318 read data strobe deassertion width 3 hack read deassertion width ?9.9?ns 319 read data strobe deassertion width 3 after ?last data register? reads 4,5 , or between two consecutive cvr, icr, or isr reads 6 hack deassertion width after ?last data register? reads 4,5 2 t c + 6.6 16.6 ? ns vih vil 116 117 118 119 118 tck (input) tdi tms (input) tdo (output) tdo (output) tdo (output) input data valid output data valid output data valid
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 36 320 write data strobe assertion width 7 hack write assertion width ? 13.2 ? ns 321 write data strobe deassertion width 7 hack write deassertion width ? after icr, cvr and ?last data register? writes 4 2 t c + 6.6 16.6 ? ns ? after ivr writes, or ? after txh:txm writes (with hbe=0), or ? after txl:txm writes (with hbe=1) ?16.5? 322 has assertion width ? 9.9 ? ns 323 has deassertion to data strobe assertion 8 ?0.0?ns 324 host data input setup time before write data strobe deassertion 7 host data input setup time before hack write deassertion ?9.9?ns 325 host data input hold time after write data strobe deassertion 7 host data input hold time after hack write deassertion ?3.3?ns 326 read data strobe assertion to output data active from high impedance 3 hack read assertion to output data active from high impedance ?3.3?ns 327 read data strobe assertion to output data valid 3 hack read assertion to output data valid ??24.2ns 328 read data strobe deassertion to output data high impedance 3 hack read deassertion to output data high impedance ??9.9ns 329 output data hold time after read data strobe deassertion 3 output data hold time after hack read deassertion ?3.3?ns 330 hcs assertion to read data strobe deassertion 3 t c + 9.9 14.9 ? ns 331 hcs assertion to write data strobe deassertion 7 ?9.9?ns 332 hcs assertion to output data valid ? ? 19.1 ns 333 hcs hold time after data strobe deassertion 8 ?0.0?ns 334 address (ad7?ad0) setup time before has deassertion (hmux=1) ? 4.7 ? ns 335 address (ad7?ad0) hold time after has deassertion (hmux=1) ? 3.3 ? ns 336 a10?a8 (hmux=1), a2?a0 (hmux=0), hr/w setup time before data strobe assertion 8 ?read ?0?ns ? write ?4.7? 337 a10?a8 (hmux=1), a2?a0 (hmux=0), hr/w hold time after data strobe deassertion 8 ?3.3?ns 338 delay from read data strobe deassertion to host request assertion for ?last data register? read 3, 4, 9 t c 5.0 ? ns table 18. hdi24 timing parameters (continued) no. characteristics 2 expression 200 mhz unit min max
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 37 339 delay from write data strobe deassertion to host request assertion for ?last data register? write 4, 7, 9 2 t c 10.0 ? ns 340 delay from data strobe assertion to host request deassertion for ?last data register? read or write (hrod = 0) 4, 8, 9 ??19.1ns 341 delay from data strobe assertion to host request deassertion for ?last data register? read or write (hrod = 1, open drain host request) 4, 8, 9, 10 ? ? 300.0 ns 342 delay from dma hack deassertion to horeq assertion ns ? for ?last data register? read 4 2 t c + 19.1 29.1 ? ? for ?last data register? write 4 1 t c + 19.1 24.1 ? ? for other cases ? 0.0 ? 343 delay from dma hack assertion to horeq deassertion ?hrod = 0 4 ??20.2ns 344 delay from dma hack assertion to horeq deassertion for ?last data register? read or write ? hrod = 1, open drain host request 4, 10 ? ? 300.0 ns notes: 1. in the timing diagrams that follow, the controls pins are drawn as active low. the pin polarity is programmable. 2. v cc = 1.0 v 10%; t j = ?40c to +125c; c l = 50 pf. 3. the read data strobe is hrd in the dual data strobe mode and hds in the single data strobe mode. 4. the ?last data register? is t he register at address $7, which is the last lo cation to be read or written in data transfers. 5. this timing is applicable only if a read from the ?last data regi ster? is followed by a read from the rxl, rxm, or rxh regist ers without first polling rxdf or hreq bi ts, or waiting for the assertion of the horeq signal. 6. this timing is applicable only if two consecutive reads from one of these registers are executed. 7. the write data strobe is hwr in the dual data strobe mode and hds in the single data strobe mode. 8. the data strobe is host read (hrd) or host write (hwr) in the dual data strobe mode and host data strobe (hds) in the single data strobe mode. 9. the host request is horeq in the single host request mode and hrrq and htrq in the double host request mode. 10. in this calculation, the host request signal is pull ed up by a 4.7 kw resistor in the open-drain mode. 11. hdi24_1 specs match those of hdi24. table 18. hdi24 timing parameters (continued) no. characteristics 2 expression 200 mhz unit min max
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 38 figure 29. hdi24 host interrupt vector register (ivr) read timing diagram figure 30. hdi24 read timing diagram, non-multiplexed bus 329 317 318 328 326 327 hack hd23 ? hd0 horeq 327 332 319 318 317 330 329 337 336 328 326 338 341 340 333 ha0 ? ha2 hcs hrd , hds hd0 ? hd23 horeq , hrrq , htrq
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 39 figure 31. hdi24 write timing diagram, non-multiplexed bus 336 331 337 321 320 324 325 339 340 341 333 ha0 ? ha2 hcs hwr , hds hd0 ? hd23 horeq , hrrq , htrq
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 40 figure 32. hdi24 read timing diagram, multiplexed bus 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 322 ha8 ? ha10 has hrd , hds had0 ? had23 horeq , hrrq , htrq address data
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 41 figure 33. hdi24 write timing diagram, multiplexed bus figure 34. hdi24 host dma write timing diagram 320 321 325 324 335 341 339 336 334 340 322 323 ha8 ? ha10 has hwr , hds had0 ? had23 horeq , hrrq , htrq address data horeq (output) hack (input) h0?h23 (input ) 320 321 343 342 324 344 325 txh/m/l write data valid
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 42 figure 35. hdi24 host dma read timing diagram 2.2.10 s/pdif timing see table 19 for sony/philips digital interconnect format (s/pdif) tim ing parameters and figure 36 and figure 37 for timing diagrams. table 19. s/pdif timing parameters characteristics symbol all frequency unit min max spdifin1, spdifin2, spdifin3, spdifin4 skew: asynchronous inputs, no specs apply ??0.7ns spdifout1,spdifout2 output (load = 50 pf) ?skew ? transition risng ? transition falling ? ? ? ? ? ? 1.5 24.2 31.3 ns spdifout1, spdifout2 output (load = 30 pf) ?skew ? transition risng ? transition falling ? ? ? ? ? ? 1.5 13.6 18.0 ns srck period srckp 40.0 ? ns srck high period srckph 16.0 ? ns srck low period srckpl 16.0 ? ns stclk period stclkp 40.0 ? ns stclk high period stclkph 16.0 ? ns stclk low period stclkpl 16.0 ? ns 326 317 318 327 328 329 horeq (output) hack (input) h0-h23 (output) data valid rxh read 342 342 343
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 43 figure 36. s/pdif srck timing diagram figure 37. s/pidf stclk timing diagram 2.2.11 emc timing (DSP56720 only) the dsp56721 device does not have an emc module. for emc timing parameters in DSP56720 devices, see table 20 , table 21 , and table 22 ; for timing diagrams, see figure 38 , figure 39 , and figure 40 . table 20. emc timing parameters (emc pll enabled; lcrr[clkdiv] = 2) parameter symbol min max unit lclk cycle time t clk 10 ? ns lclk skew to lsync_out t clk_skew ? 160 ps input setup to lsync_in (except lgta /lupwait) t in_s 2?ns input hold from lsync_in (except lgta /lupwait) t in_h 2?ns lgta valid time t gta 12 ? ns lupwait valid time t upwait 12 ? ns lale negedge to lad(address phase) invaild (address latch hold time) t ale_h 3?ns lale valid time t ale 3.8 ? ns output setup from lsync_in (except lad[23:0] and lale) t out_s 4?ns output hold from lsync_in (except lad[23:0] and lale) t out_h 2?ns lad[23:0] output se tup from lsync_in t ad_s 3.5 ? ns lad[23:0] output hold from lsync_in t ad_h 1.5 ? ns lsync_in to output high impedance for lad[23:0] t ad_z ?4.3ns srck (output ) srckp srckph srckpl v m v m stclk (input) stclkp stclkph stclkpl v m v m
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 44 figure 38. emc signals (emc pll enabled; lcrr[clkdiv] = 2) t in_s t in_h lgta asynchronous input la[2:0]/lbctl/lcs[7:0] loe /lwe lcke/lsda10/lsddqm lgpl[5:0] output signals lsync_in lsync_out lclk lad[23:0] (data) t clk t clk_skew lupwait asynchronous input t gta t upwait t out_s t out_h t sync_in_skew lale t ad_s t ad_h lad[23:0] t ad_z lsdwe /lsdras /lsdcas t ale t ale_h
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 45 table 21. emc timing parameters (e mc pll bypassed; lrcc[clkdiv] = 4) parameter symbol min max unit lclk cycle time t clk 20 ? ns input setup to lclk (except lgta /lupwait) t in_s 8 ? ns input hold from lclk (except lgta /lupwait) 1 t in_h -1 ? ns lgta valid time t gta 22 ? ns lupwait valid time t upwait 22 ? ns lale negedge to lad (address phase) invalid (address latch hold time) t ale_h 4 ? ns lale valid time t ale 14 ? ns output setup from lclk (except lad[23:0] and lale) t out_s 9 ? ns output hold from lclk (except lad[23:0] and lale) t out_h 8 ? ns lad[23:0] output setup from lclk t ad_s 8 ? ns lad[23:0] output hold from lclk t ad_h 7 ? ns lclk to output high impedance for lad[23:0] t ad_z ? 9ns notes: 1. a negative hold time means that the signal could be invalid before the lclk rising edge.
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 46 figure 39. emc signals (emc pll bypassed; lrcc[clkdiv] = 4) table 22. emc timing parameters (e mc pll bypassed; lrcc[clkdiv] = 8) parameter symbol min max unit lclk cycle time t clk 40 ? ns input setup to lclk (except lgta /lupwait) t in_s 8?ns input hold from lclk (except lgta /lupwait) 1 t in_h -1 ? ns lgta valid time t gta 42 ? ns lupwait valid time t upwait 42 ? ns lale negedge to lad (address phase) invalid (address latch hold time) t ale_h 5?ns lale valid time t ale 34 ? ns output setup from lclk (except lad[23:0] and lale) t out_s 19 ? ns output hold from lclk (except lad[23:0] and lale) t out_h 18 ? ns t in_s t in_h lgta btzodispopvt input la[2:0]/lbctl/lcs[7:0] loe /lwe lcke/lsda10/lsddqm lgpl[5:0] output signals lclk lad[23:0] (data) t clk lupwait btzodispopvt input t gta t upwait t out_s t out_h lale t ad_s t ad_h lad[23:0] t ad_z lsdwe /lsdras /lsdcas t ale t ale_h
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 47 figure 40. emc signals (emc pll bypassed; lrcc[clkdiv] = 8) lad[23:0] output setup from lclk t ad_s 18 ? ns lad[23:0] output hold from lclk t ad_h 17 ? ns lclk to output high impedance for lad[23:0] t ad_z ?19ns notes: 1. a negative hold time means that the signal could be invalid before the lclk rising edge. table 22. emc timing parameters (emc p ll bypassed; lrcc[clkdiv] = 8) (continued) parameter symbol min max unit t in_s t in_h lgta btzodispopvt input la[2:0]/lbctl/lcs[7:0] loe /lwe lcke/lsda10/lsddqm lgpl[5:0] output signals lclk lad[23:0] (data) t clk lupwait btzodispopvt input t gta t upwait t out_s t out_h lale t ad_s t ad_h lad[23:0] t ad_z lsdwe /lsdras /lsdcas t ale t ale_h
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 48 3 functional description and application information see the DSP56720 reference manual (DSP56720rm) for detailed functional and applications information. 4 hardware design considerations for design consider ations, also see section 2.1.3, ?power requirements .? 5 ordering information table 23 provides ordering information for both the DSP56720 and dsp56721. 6 package information for the outline drawings of available device packages, see table 24 and sections 6.1 ? 6.2 . 6.1 80-pin package outline drawing for the 80-pin package outline drawings, see figure 41 and figure 42 . table 23. ordering information product rom version package part number DSP56720 a 144-pin plastic lqfp dspa56720ag b 144-pin plastic lqfp dspb56720ag dsp56721 a 144-pin plastic lqfp dspa56721ag b 144-pin plastic lqfp dspb56721ag a 80-pin plastic lqfp dspa56721af b 80-pin plastic lqfp dspb56721af table 24. package outline drawings device package see DSP56720 144-pin plastic lqfp figure 43 on page 51 and figure 44 on page 52 dsp56721 80-pin plastic lqfp figure 41 on page 49 and figure 42 on page 50 144-pin plastic lqfp figure 43 on page 51 and figure 44 on page 52
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 49 figure 41. 80-pin package outline drawing (1 of 2)
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 50 figure 42. 80-pin package outline drawing (2 of 2)
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 51 6.2 144-pin package outline drawing for the 144-pin package drawings, see figures figure 43 and figure 44 . figure 43. 144-pin package outline drawing (1 of 2)
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 52 figure 44. 144-pin package outline drawing (2 of 2)
symphony tm DSP56720 / dsp56721 multi-core audio processors, rev.1 freescale semiconductor 53 7 product documentation this data sheet is labeled as a particular type: product previe w, advance information, or tech nical data. definitions of these types are available at: http://www.freescal e.com. documentation is available from a local freescale semiconductor, inc. distributor, semiconductor sales office, literature distribu tion center, or through the freescale dsp home page on the internet (the source for the latest information). the following documents are required for a complete description of the device and are necessary to design properly with the parts: dsp56300 family manual (document number dsp56300fm). detailed descri ption of the 56300-family architecture and the 24-bit core processor and instruction set. DSP56720/dsp56721 reference manual (document number DSP56720rm). detailed description of memory, peripherals, and interfaces. DSP56720 product brief (DSP56720pb). brief descript ion of the DSP56720 device. dsp56721 product brief (dsp56721pb). brief descript ion of the dsp56721 device. 8 revision history table 25 summarizes revisions to this document. table 25. revision history revision date description 1 december 2007 ? initial public release.
document number: DSP56720 rev.1 12/2007 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org ? freescale semiconductor, inc. 2006, 2007. all rights reserved.

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